TALKING ELECTRONICS PIC Theory Page 9

F84 Details

Features and details of the PIC16F84

Page 9
INDEX

INTRODUCTION
The PIC16F84 is a low-cost high performance, CMOS, fully static, 8-bit microcontroller. It employs a RISC (Reduced Instruction-Set Computer) architecture with only 35 single-word single-cycle instructions.

All instructions are single-cycle (1uS) for a 4MHz internal RC oscillator, except for program branches which take 2 cycles. The clock is internally divided by four to produce one Machine Cycle. Instructions are executed in one Machine Cycle. Instructions are 14-bit wide and the F84 contains 1024 address locations.

FEATURES
Only 35 single-word instructions.
All instructions are single cycle except program branches.
Operating speed: DC to 4MHz
14-bit wide instructions
8-bit wide data path
Fifteen Special Function hardware files 00h to 0Bh: (some have no address)
Eight-level stack
Direct, indirect and relative addressing modes
Four interrupt sources,:
- External RB0/INT pin
- TMR0 timer overflow
- PortB<7:4> interrupt on change
- Data EEPROM write complete
1,000,000 data memory EEPROM ERASE/WRITE cycles
EEPROM Data Retention >40 years

Peripheral Features:
13 I/O pins with individual direction control
High current sink/source
- 25mA sink per pin
- 20mA source per pin
TMR0: 8-bit timer/counter with 8-bit programmable prescaler
Special Microcontroller Features:
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
Watchdog Timer (WDT) with its own on-chip RC oscillator
Code Protection
Power saving SLEEP mode
Selectable oscillator options
Serial In-system Programming via two pins
CMOS Technology:
Low-power, high-speed CMOS Flash/EEPROM technology
Fully static design
Wide operating range: 2v to 6v
Low power consumption: < 2mA typical @5v 4MHz < 1uA standby current
68 General Purpose Registers (files): 0Ch to 4F.
1024 address locations for program: 000 to 3FF
The ALU (Arithmetic Logic Unit) is 8-bits wide and capable of addition, subtraction, shift and logical operations.
The W (working) register is an 8-bit working register. It accepts data (called constants, literals or numbers) and transfers these values from one file to another.
It also performs logic operations but is not an addressable register. (You cannot bit-test or shift the contents etc.)

PIN DESCRIPTION:

Pin 1: RA2. Bi-directional I/O line.
Pin 2: RA3. Bi-directional I/O line.
Pin 3: RA4/T0CKI. Bi-directional I/O line. Can also be selected as clock input for TMR0 timer/counter. Output is open drain type.
Pin 4: MCLR. Master clear (reset) input/programming voltage input. Active low to reset the chip.
Pin 5: Vss. Ground.
Pin 6: RB0/INT. Bi-directional I/O line. Can be selected as external interrupt pin.
Pin 7: RB1. Bi-directional I/O line.
Pin 8: RB2. Bi-directional I/O line.
Pin 9: RB3. Bi-directional I/O line.
Pin 10: RB4. Bi-directional I/O line. Interrupt on change pin.
Pin 11: RB5. Bi-directional I/O line. Interrupt on change pin.
Pin 12: RB6. Bi-directional I/O line. Interrupt on change pin. Serial program Clock
Pin 13: RB7. Bi-directional I/O line. Interrupt on change pin. Serial program Data
Pin 14: Vdd Positive supply
Pin 15: Osc2/ClkOut Oscillator crystal output
Pin 16: Osc1/ClkIn Oscillator crystal input. External clock input
Pin 17: RA0. Bi-directional I/O line.
Pin 18: RA1. Bi-directional I/O line

MEMORY ORGANISATION

PIC16F84 memory is organised into:
PROGRAM MEMORY and DATA MEMORY.

PROGRAM MEMORY
There are 1024 PROGRAM MEMORY locations. This is equivalent to 4 pages (a page is 000 to 0FF) or 1K of memory.

RESET VECTOR
The reset vector is at 000h and the interrupt vector is at 004h.

ADDRESSING PROGRAM MEMORY
Program memory cannot be altered but can contain bytes of data in the form of tables. Each byte of data must include the instruction RETLW. e.g:

RETLW 3Ah

DATA MEMORY
DATA MEMORY is partitioned into two areas. The first is the Special Function Registers (FSR) area and the second is the General Purpose Registers (GPR) area. The FSR’s control the operation of the chip.
Portions of data memory are banked. This is for both the FSR area and the GPR area. The GPR area is banked to allow greater than 116 bytes of general purpose RAM. The banked areas of the FSR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection.
These control bits are located in the STATUS register.
Instructions MOVWF and MOVF can move values from the W register to any location in the register file, and vice-versa.
The entire data memory can be addressed either directly using the absolute address of each register file or indirectly through the File Select register (FSR). Indirect addressing uses the present value of the RP1:RP0 bits for access into the banked area of data memory.
Data memory is partitioned into two banks that contain the General Purpose Registers and the Special Function Registers. Bank 0 is selected by clearing the RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank 1. The first twelve locations of each bank are reserved for the Special Function Registers. The remainder are General Purpose Registers implemented as static RAM.

GENERAL PURPOSE REGISTER FILE
Each GPR is 8 bits wide and is accessed either directly or indirectly through the FSR. There are 68 GPR’s. They are located at 0Ch to 4F. These are the files used by the programmer when writing a program.

SPECIAL FUNCTION REGISTERS
The Special Function Registers are used by the CPU and peripheral functions to control the operation of the chip. These registers are static RAM. They are located at 00h to 0Ch and contain Port A (file 05) and Port B (file 06).

Address	Name	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Bank 0
00h	INDF	Uses contents of FSR to address data memory
01h	TMR0	8-bit real-time clock/counter
02h	PCL	Low-order 8-bits of Program Counter
03h	STATUS	IRP	RP1	RP0	TO	PD	Z	DC	C
04h	FSR	Indirect data memory address pointer
05h	PORT A	-	-	-	RA4/TOC1	RA3	RA2	RA1	RA0
06h	PORT B	RB7	RB6	RB5	RB4	RB3	RB2	RB1	RB0
08h	EEDATA	EEPROM data register
09h	EEADR	EEPROM address register
0Ah	PCLATH	-	-	-	Write buffer for upper 5 bits of the PC
0Bh	INTCON	GIE	EEIE	T0IE	INTE	RBIE	T0IF	INTF	RBIF
Bank 1
80h	INDF	Uses contents of FSR to address data memory
81h	OPTION	RBPU	INTEDG	T0CS	T0SE	PSA	PS2	PS1	PS0
82h	PCL	Low order 8 bits of Program Counter
83h	STATUS	IPR	RP1	RP0	TO	PD	Z	DC	C
84h	FSR	Indirect data memory address pointer 0
85h	TRIS A	-	-	-	PORT A data direction register
86h	TRIS B	PORT B data direction register
88h	EECON1	-	-	-	EEIF	WRERR	WREN	WR	RD
89h	EECON2	EEPROM Control Register
0Ah	PCLATH	-	-	-	Write buffer for upper 5 bits of the PC
0Bh	INTCON	GIE	EEIE	T0IE	INTE	RBIE	T0IF	INTF	RBIF
SPECIAL FUNCTION REGISTER SUMMARY

R/W-0	R/W-0	R/W-0	R-1	R-1	R/W-x	R/W-x	R/W-x
IRP	RP1	RP0	TO	PD	Z	DC	C
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
STATUS REGISTER Address 03h				R = Readable bit W = Writable bit -0 = Value at Power On Reset

STATUS REGISTER (Address 03h)
The STATUS register contains the arithmetic status of the ALU (Arithmetic Logic Unit), the RESET status and the bank select bit for data memory.

Bit 7: IRP: Register Bank Select bit (used for indirect addressing)
0 = Bank 0,1 (00h - FFh)
1 = Bank 2,3 (100h - 1FFh)
The IRP bit is not used by PIC16F84. It should be kept clear.
Bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
Each bank is 128 bytes. Only bit RP0 is used by the PIC16F84. Keep RP1 clear
Bit 4: TO. Time-out bit.
1 = After power-up, CLRWDT instruction, or SLEEP.
0 = A WDT time-out occurred
Bit 3: PD Power-down bit.
1 = After power-up or by the CLRWDT instruction.
0 = By execution of SLEEP instruction
Bit 2: Z = Zero bit
1 = The result of an arithmetic or logic operation is zero.
0 = The result of an arithmetic or logic operation is not zero.
Bit 1: DC Digit carry/borrow (for ADDWF and SUBWF instructions)
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur.
Bit 0: C: Carry/borrow (for ADDWF, ADDLW instructions).
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the second register.

R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1	R/W-1
RBPU	INTEDG	T0CS	T0SE	PSA	PS2	PS1	PS0
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
OPTION REGISTER				R = Readable W = Writable bit -n = Value at Power On Reset

OPTION REGISTER (address 81h)
The OPTION register is an 8-bit wide, readable, writable register containing various control bits to configure the TMR0/WDT prescaler, the external INT interrupt, TMR0, and the weak pull-ups on PORT B.
Bit 7: RBPU: PORTB pull-up Enable bit
1 = PORT B pull-ups are disabled
0 = PORT B pull-ups are enabled (by individual port latch values)
Bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
Bit 5: T0CS: Timer0 clock source select bit
1 = Transition on RA4/T0CKI pin.
0 = Transition on internal instruction cycle clock, (ClkOut)
Bit 4: T0SE: Timer0 source edge select bit.
1 = Increment on high to low transition on RA4/T0CKI pin.
0 = Increment on low to high transition on RA4/T0CKI pin.
Bit 3: PSA: Prescaler Assignment pin.
1 = Prescaler assigned to the WDT.
0 = Prescaler assigned to Timer0.
Bits 2-0 are: PS2, PS1 and PS0. These are the pre-scaler bits for Timer0 and WDT as shown below:

Bit Value	Timer0 Rate	WDT Rate
000	1:2	1:1
001	1:4	1:2
010	1:8	1:4
011	1:16	1:8
100	1:32	1:16
101	1:64	1:32
110	1:128	1:64
111	1:256	1:128

R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
GIE	EEIE	T0IE	INTE	RBIE	T0IF	INTF	RBIF
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
INTECON REGISTER				R = Readable W = Writable bit -n = Value at Power On Reset

INTCON REGISTER (address 0Bh, 8Bh)
The INTECON register is an 8-bit wide, readable and writable register containing various enable bits for all interrupt sources.
Bit 7: GIE: Global Interrupt Enable bit
1 = Enable all un-masked interrupts
0 = Disables all interrupts
Bit 6: EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
Bit 5: T0IE TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
Bit 4: INTE: RB0/INT Interrupt Enable bit
1 = Enables the RB0/INT interrupt
0 = Disables the RB0/INT interrupt
Bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
Bit 2: T0IF: TMR0 overflow interrupt flag bit
1 = TMR0 has overflowed (must be cleared in software)
0 = The TMR0 did not overflow
Bit 1: INTF: RB0/INT Interrupt flag bit
1 = The RB0/INT Interrupt occurred
0 = The RB0/INT Interrupt did not occur
Bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed stage ( clear in software)
0 = None of the RB7:RB4 pins have changed state.

PROGRAM COUNTER
As a program instruction is executed, the Program Counter (PC) will contain the address of the next instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL) When doing a table read using a computed GOTO method, the table should not go over a page boundary (each 256 word block).

THE STACK
The PIC16F84 has an 8-deep, 13-bit wide push/pop stack. The entire 13-bit PC is pushed onto the stack when a call instruction is executed or an interrupt is acknowledged. The stack is popped in the event of a RETURN, RETLW or RETFIE instruction execution. PCLATH is not affected by a push or pop operation.
The stack operates as a circular buffer. After the stack has been pushed 8 times, the ninth push overwrites the value of the first push etc. If the stack is popped nine times the PC value is the same as the first pop.

INDIRECT DATA ADDRESSING
INDF and FSR Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register.
This is INDIRECT ADDRESSING.
See Indirect Addressing in Library of Terms and Routines for examples.

I/O PORTS
The PIC16F84 has two ports, PORT A and PORT B. Some pins are multiplexed with an alternate function for other features.

PORT A and TRIS A Registers
Port A is a 5-bit wide latch. RA4 is a Schmitt Trigger input and an open drain output. All other PORT A pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS Registers) that can configure the pins as input or output.
Setting a TRIS bit (=1) will make the corresponding “PORT A” pin an input. (It puts the corresponding output driver into high impedance mode). Clearing a TRIS A bit (=0) will make the corresponding “PORT A” pin an output.
Reading the “PORT A” register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. So a write to a port implies that the port pins are first read, then this value is modified and written to the port data latch. RA4 pin is multiplexed with the TMR0 clock input.

PORT B and TRIS B Registers
PORT B is an 8-bit wide bi-directional port. The corresponding data direction register is TRIS B. A “1” on any bit in the TRIS B register puts the corresponding output driver in a high-impedance mode. A “0” on any bit in the TRIS B register puts the contents of the output latch on the selected pin(s).
Each of the PORT B pins has a weak internal pull-up resistor. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU (OPTION<7>) bit. The weak pull-up is automatically turned off when the port pin is configured as an input. The pull-ups are disabled on Power-On Reset.
Four of PORT B’s pins RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can cause this interrupt to occur.
The pins value in input mode are compared with the old value latched on the last read of PORT B. The “mismatch” output of the pins are OR’ed together to generate a RB port change interrupt.
This interrupt can wake the chip from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:
a) Read (or write) PORTB. This will end the mismatch condition.
b) Clear flag bit RBIF
A mismatch condition will continue to set the RBIF bit. Reading PORT B will end the mismatch condition and allow RBIF bit to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-press.

I/O PROGRAMMING CONSIDERATIONS

BI-DIRECTIONAL PORTS
Any instruction that writes, operates internally as a read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register.
Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions, (i.e: BCF, BSF etc) on a port, the value of the port pins is read, the desired operation is done to this value and this value is then written to the port latch.
A pin actively outputting a LOW or HIGH should not be driven from an external device at the same time in order to change the level on the pin. The resulting high output current may damage the chip.

SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle. Therefore care must be exercised if a write followed by a read operation is carried out on the same I/O port. The two instructions should be separated with a NOP.

TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
- 8-bit timer/counter register TMR0, readable and writable.
- 8-bit software programmable prescaler
- internal or external clock select
- edge select for external clock
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit (OPTION<<5>>). In this mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the T0 source edge select bit, T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4 . . . 1:256 are selectable.

TMR0 INTERRUPT
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets the T0IF bit (INTCON<2>). The interrupt can be masked by clearing enable bit T0IE (INTCON<5>). The T0IF bit must be cleared in software by the Timer0 Module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP.

USING TIMER0 WITH EXTERNAL CLOCK
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronisation. Also, there is a delay in the actual incrementing of Timer0 after synchronisation.

EXTERNAL CLOCK SYNCHRONISATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronisation of RA4/T0CKI with the internal phase clock is accomplished by sampling the prescaler output on the second and fourth cycles of the internal phase clocks (the oscillator is divided by four to produce a machine clock cycle). Therefore it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20nS) and low for at least 2Tosc (and a small RC delay of 20nS). When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore it is necessary for T0CKI to have a period of least 4Tosc (and a small RC delay) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10nS.

TIMER0 INCREMENT DELAY
Since the prescaler output is synchronised with the internal clocks, there is a small delay from the time the external clock edge occurs to the time when Timer0 module is actually incremented.

PRESCALER
An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT). For simplicity, this counter is being referred to as "prescaler." Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice versa.
The PSA and PS2:PS0 bits (OPTION <<3:0>>) determine prescaler assignment and prescaler ratio.
When assigned to the Timer0 module, all instructions to the TMR0 register (e.g: CLRF 01 MOVWF 01 BSF 01,x etc) will clear the prescaler. When assigned to WDT a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable of writable. On a RESET, the prescaler contains all 0's.

SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (it can be changed during program execution). To avoid an unintended device RESET an instruction sequence must be executed when changing the prescaler assignment from Timer0 to the WDT.

DATA EEPROM MEMORY
The EEPROM data memory is readable and writable during normal operation. This memory is not directly mapped in the register file space. Instead it is indirectly addressed through the Special Function Registers. There are four SFR’s used to read and write this memory.
These registers are:
EECON1
EECON2
EEDATA
EEADR
EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. The PIC16F84 has 64 bytes of data EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles. The write time will vary with the voltage and temperature.
When the device is code protected, the CPU may continue to read and write the data EEPROM memory. The device programmer can no longer access this memory.

EEADR
The EEADR register can address up to a maximum of 256 bytes. Only the first 64 bytes of EEPROM are implemented.

EECON1 and EECON2 Registers
EECON1 is the control register with 5 low order bits physically implemented. The upper 3 bits are non-existent and read as “0’s.”
Control bits RD and WR initiate read and write. These bits cannot be cleared, only set, in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.
The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR reset or a WDT time-out reset during normal operation. In these situations, following reset, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers.
Interrupt flag bit EEIF is set when write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2 will read all “0’s.” The EECON2 register is used exclusively in the Data EEPROM write sequence.

Reading the EEPROM Data Memory
To read a data memory location. The user must write the address to the EEDDR register and then set control bit RD (EECON1<0>). The data is available, in the very next cycle, in the EEDATA register, therefore it can be read in the next instruction. EEDATA will hold this value until another read or until it is written to by the user.

Writing to the EEPROM Data Memory
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then the user must follow a specific sequence to initiate the write for each byte, thus:

	BSF STATUS, RP0	;Bank 1
	BCF INTCON, GIE	;Disable Interrupts
	BSF EECON1, WREN	;Enable Write
	MOVLW 55h	;
	MOVWF EECON2	;Write 55h
	MOVLW AAh	;
	MOVWF EECON2	;Write AAh
	BSF EECON1, WR	;Set WR bit Begin write
	BSF INTCON, GIE	;Enable Interrupts

The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. Interrupts should be disabled during this code segment.
The WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental write to data EEPROM due to unexpected code execution. The WREN bit should be kept clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.

Write Verify
Depending on the application, good programming may dictate that the value written to the Data EEPROM should be verified.

	BCF STATUS, RP0	;Bank 0
		; Your code goes here
	MOVF EEDATA, W	;Must be in Bank 0
	BSF STATUS, RP0	;Bank 1
	BSF EECON1, RD	;Yes, read the value written
	BCF STATUS RP0	;Bank 0
	SUBWF EEDATA, W	;Is the value written (in W ) and read (in EEDATA) the same?
	BTFSS STATUS,Z	;Is difference 0?
	GOTO WRITE_ERR	;No. Write error
		;Yes. Good write, continue program

Protection Against Spurious Writes
There are conditions when the chip may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, on power-up, WREN is cleared and the Power-up timer (72mS duration) prevents EEPROM write.
When the chip is code protected, the CPU is able to read and write unscrambled data to the data EEPROM.

SPECIAL FEATURES OF THE CPU:
- Oscillator selection
- Power On Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)

Interrupts
- Watchdog Timer (WDT)
- SLEEP
- Code protection
- ID Locations
- In-circuit serial Programming

The PIC16F84 has a Watchdog Timer that can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability.
There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Power-up timer (PWRT), which provides a fixed delay of 72mS on power-up only. This keeps the device in reset while the power supply stabilises.
With these timers, most applications need no external reset circuitry.
The SLEEP mode is designed to offer a very low current power-down mode. The user can wake up from SLEEP through external reset, Watchdog Timer time-out, or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

CONFIGURATION BITS
The configuration bits can be programmed (read as “0”) or left unprogrammed (read as “1”) to select various device configurations.

OSCILLATOR CONFIGURATIONS
The PIC16F84 can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC2) to select one of these four modes:

- LP: Low Power Crystal
- XT: Crystal/Resonator
- HS: High Speed Crystal/Resonator
- RC: Resistor/Capacitor

CRYSTAL OSCILLATOR/CERAMIC RESONATOR
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/ClkOut pins to establish oscillation. The oscillator design requires the use of a parallel cut crystal.
When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin.

EXTERNAL CRYSTAL OSCILLATOR
Either a pre-packaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator. Pre-packaged arrangements offer a wide operating range and better stability.
A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

RC OSCILLATOR
For timing insensitive applications, the RC option offers additional savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) and the operating temperature. In addition, the oscillator frequency will vary from unit to unit to parameter variations.
The difference in frame capacitance between package types will also affect the frequency.
For Rext below 2k2, the oscillator may stop completely. For values above 1M, the oscillator becomes sensitive to noise, humidity and leakage. Rext should be between 3k3 and 100k. Although the oscillator will operate with no external capacitor, a value above 20p should be used for noise and stability reasons.

RESET
The device differentiates between various kinds of reset:
(a) Power On Reset (POR)
(b) MCLR reset during normal operation
(c) MCLR reset during SLEEP
(d) WDT time-out reset during normal operation
(e) WDT time-out during SLEEP
(f) Wake-up from SLEEP on pin change

Some registers are not reset in any way, they are unknown on POR and are unchanged in any other reset. Most other register are reset to "reset state" on power-on reset (POR), on MCLR or WDT reset during normal operation. They are not affected by a WDT reset during SLEEP or MCLR reset during SLEEP, since these resets are viewed as resumptions of normal operation. The exceptions to this are TO PD and GPWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of the reset.

Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range 1.2v to 1.7v). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. An internal weak pull-up resistor is implemented using a transistor. This will eliminate external RC components usually needed to create power-on Reset. A minimum rise time for VDD must be met for this to operate properly. When the chip starts normal operation, (exits the reset condition) device operating parameters (voltage, frequency, temperature) must be met to ensure operation. If not, the chip must be held in reset until the conditions are met.

Power-up Timer
The Power-up Timer (PWRT) provides a fixed 72mS time-out from POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active. A configuration bit, PWRTE, can enable/disable the PWRT.

Oscillator Start-up Timer
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle delay (from OSC1 input) after the PWRT delay ends. This ensures the crystal oscillator or resonator has stabilised.
The OST time-out (Tosc) is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

Time-out Sequence and Power-down Status Bits
On power-up, the time-out sequence is as follows: First the PWRT time-out is invoked after a POR has expired. Then the OST is activated. The total time-out will vary based on oscillator configuration and PWRTE configuration bit status.
Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then bringing MCLR high, excursion will begin immediately.

Interrupts
The PIC16F84 has 4 sources of interrupt:
- External interrupt RB0/INT pin
- TMR0 overflow interrupt
- PORT B change interrupts (pins RB7:RB4)
- Data EEPROM write complete interrupt.

The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also contains the individual and global interrupt enable bits.
The global interrupt enable bit, GIE (INTCON<7>) enables (if set) all unmarsked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in INTCON register. Bit GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits interrupt routine as well as sets the GIE bit, which re-enable interrupts.
The RB0/INT pin interrupt, the RD port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register.
When an interrupt is responded to; the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. For external interrupt events, such as the RB0/INT pin or PORT B change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for both one and two cycle instructions. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid infinite interrupt requests.

INT Interrupt
External interrupt on RB0/INT pin is edge triggered: either rising if INTEDG bit (OPTION<6>) is set or falling, if INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, the INTF bit (INTCON<1>) is set. This interrupt can be disabled by clearing control bit INTE (INTCON<4>). Flag bit INTF must be cleared in software via the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake the processor from SLEEP only if the INTE bit was set prior to going into SLEEP. The status of the GIE bit decides whether the processor branches to the interrupt vector following wake-up.

TMR0 Interrupt
An overflow (FFh to 00h) in TMR0 will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/ disabled by setting/clearing enable bit T0IE (INTCON<5>).

PORT RB Interrupt
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit (INTCON<3>).

Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users wish to save key register values during an interrupt. This is implemented in software.

WATCHDOG TIMER
The Watchdog Timer (WDT) is a free-running on-chip RC oscillator which does not require any external components. It is separate from the external RC oscillator of the OCS1/CLKIN pin and the internal 4MHz oscillator. This means the WDT will run even if the clock on the OCS1/CLKIN and OSC2/ClkOut pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out guarantees a device reset. If the chip is in SLEEP mode, a WDT Wake-up causes the chip to wake up and continue with normal operation. The WDT can be permanently disabled by programming the configuration bit WDTE as "0."

WDT PERIOD
The WDT has a normal time-out period of 18mS (with no prescaler). If a longer time-out period is required, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the Option register. Thus a time-out period up to approx 2.3 seconds can be realised. The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT and prevents it from timing out and generating a device reset. The TO bit in the STATUS register will be cleared upon a WDT time-out.

POWER-DOWN MODE (SLEEP)
A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).

SLEEP
The power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog timer will be cleared but keeps running, the TO bit (status bit 4) is set, the PD bit (Status bit 3) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving HIGH, driving LOW or Hi-impedance).

For the lowest current consumption in SLEEP mode, place all I/O pins at either Vdd or Vss with no external circuitry drawing current from the pins, and disable external clocks. I/O pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at Vdd or Vss.
The MCLR pin must be at logic high level. A reset generated by WDT time-out does not drive MCLR pin low.

Wake-Up from SLEEP
The device can wake-up from SLEEP through one of the following events:
1. An external reset input on MCLR/Vpp pin.
2. A Watchdog Timer wake up (if WDT was enabled).
3. Interrupt from RB0/INT pin, RB port change, or data EEPROM write complete.
Peripherals cannot generate interrupts during SLEEP, since no on-chip Q clocks are present.
The first event (MCLR reset) will cause a device reset. The TO and PD bits can be used to determine the cause of a chip reset. The PD bit which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred (and caused wake-up).

While the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the chip to wake up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake up occurs regardless of the state of the GIE bit. If the GIE bit is cleared (disabled) the chip continues execution at the instruction after the SLEEP instruction. If the GIE bit is set, (enabled) the chip executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h).

WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag set, one of the following will occur:
If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore the WDT and WDT postscaler will not be cleared, the /TO bit will not be set and PD bit will not be cleared.
If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be clear.

Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine if a SLEEP instruction completes, test the PD bit. If it is set, the SLEEP instruction was executed as a NOP.

PROGRAM VERIFICATION CODE PROTECTION
If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes.

ID LOCATIONS
Four memory locations are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Only the lower 4 bits of ID location are usable.

In-Circuit Serial Programming
The PIC16F84 can be serially programmed in the end-application circuit. This is done with lines for: clock, data, power, ground and the programming voltage.
The chip is placed in program/verify mode by holding the RB6 and RB7 pins low, while raising the MCLR pin from V_IL to V_IHH. RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the chip into program/verify mode, the Program Counter points to location 00h. A 6-bit command is then sent to the chip, 14 bits of program data is then supplied to or from the chip using load or read instructions.

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